1. Field of the Invention
The present invention relates to a transmission device which performs prescribed processing of signals in a plurality of channels, and transmits signals in the plurality of channels, and a data processing method and data conversion method in this transmission device. The present invention further relates to a program product to cause a computer to execute data processing and data conversion in a transmission device which performs prescribed processing of signals in a plurality of channels, and transmits signals in the plurality of channels.
2. Description of the Related Art
In a communication system, devices in which realtime processing is required conventionally are generally realized through dedicated hardware circuits in order to perform high-speed processing. For example, line switching control units in bi-directional line switched ring (BLSR) systems using the SONET/SDH (Synchronous Optical Network/Synchronous Digital Hierarchy) transmission method are required to perform realtime processing, and so conventionally have been realized using dedicated hardware circuits.
FIG. 21A is a block diagram showing the configuration of a BLSR system using the SONET/SDH transmission method. This BLSR system has, for example, six nodes, n1 to n6, in a 4BLSR system in which four optical fibers (cores) are connected between each node. Of the four fibers, two are used as work lines (Work), and the remaining two are used as protection lines (PTCT). One of the work lines and one of the protection lines are used to transmit optical signals in the clockwise direction; the remaining lines are used to transmit optical signals in the counterclockwise direction.
A plurality of channels are multiplexed using time slots (time-division multiplexing) and transmitted in one optical fiber. For example, in the case of OC (Optical Carrier)-48, channels ch1 to ch48 are multiplexed; in the case of OC-192, channels ch1 to ch192 are multiplexed.
In the state in which there are no faults in any optical fibers or nodes (the normal state), signals (the main signal) are transmitted in the work line. However, when a fault occurs in an optical fiber or in a node, switching processing is executed by an APS (Automatic Protection Switching) protocol, and the main signal is transmitted in the protection line. Specifically, according to the circumstances of the fault, a span-switch and span-bridge, or a ring-switch and ring-bridge, are executed at the node.
FIG. 21B shows switching processing for the case in which a fault has occurred in the four optical fibers between nodes n2 and n3 in the BLSR system of FIG. 21A. When a fault occurs between nodes n2 and n3, a loop-back (a ring-switch and ring-bridge in each of the east side in node n2 and the west side in node n3) is executed by the APS protocol, in an attempt to salvage the main signal.
Though not shown in the figure, if a fault occurs only in the work line between nodes n2 and n3, instead of a loop-back, a span-switch and span-bridge are executed in which the main signal of the work line between nodes n2 and n3 is switched to the protection line in the same direction between nodes n2 and n3, in an attempt to salvage the main signal. For example, if a fault occurs in the work line from node n2 to node n3, a span-bridge is executed on the east side of node n2, and the main signal is transmitted via the protection line to node n3. And, a span-switch is executed on the west side of node n3, to return the main signal input from the protection line to the work line side.
Such switching processing in the nodes by the APS protocol is executed by a line switching control unit provided at each node. FIG. 22 is a block diagram showing in summary the configuration of nodes n1 to n6 in a BLSR system.
Each node has a host processor 1; a line switching control unit 200; a span-switch unit 3; a ring-switch unit 4; a span-bridge unit 5; and a ring-bridge unit 6. The span-switch unit 3 has selection circuits 31 and 32, and AIS (Alarm Indicated Signal) insertion circuits 33 and 34. The ring-switch unit 4 has selection circuits 41 and 42; the span-bridge unit 5 has selection circuits 51 and 52; and the ring-bridge unit 6 has selection circuits 61 and 62.
Though not shown in the figure, within each node the main signal is processed as an electrical signal, so that at the input terminal, a photoelectric converter to convert optical signals input from the optical fiber into electrical signals is provided, and at the output terminal, a photoelectric converter to convert electrical signals into optical signals is provided. A switch unit to perform time slot switching (exchanging) is also provided.
The host processor 1 manages node operation; holds information relating to faults according to the APS protocol which is communicated between nodes, information on the initial settings of the device, and other information; and sends this information as control data to the line switching control unit 200.
The line switching control unit 200 is configured from dedicated hardware circuitry. The line switching control unit 200 generates control signals to control each of the selection circuits and/or AIS insertion circuits of the span-switch unit 3 to the ring-bridge unit 6, based on control data sent by the host processor 1, and sends the control signals to these circuits.
Based on these control signals, the selection circuits 31, 32, 41, 42, 51, 52, 61, and 62 select and output one main signal from the two main signals input. The AIS insertion circuits 33 and 34 output an AIS based on control signals, and insert the AIS into the main signal. By this means, normal transmission/reception of main signals, as well as switching processing (ring-switch and ring-bridge, or span-switch and span-bridge processing) upon occurrence of a fault, are executed.
For example, at the span switch and span bridge, the work line channels are switched with the protection line channels in the same direction, and an AIS is inserted into the protection line channels. At the ring switch and ring bridge, the work line channels are switched with the protection line channels in the opposite direction.
However, when hardware circuitry is used to realize a line switching unit, it is necessary to redesign and remanufacture hardware each time there is a change in the recommended specifications of the ITU-T or similar, or a small-scale modification, addition, or functional upgrade of specifications. Consequently development time is lengthened, and costs are increased.
On the other hand, rapid product development and shipment is also required. Hence there is a need to realize in software, rather than in hardware circuitry, the functions of a line switching control unit, which is required to perform realtime processing, and to develop an inexpensive device in a short period of time.
FIG. 23 is a block diagram showing the conventional configuration of the line switching control unit 200 for the case in which processing by the line switching control unit 200 is realized in software. The line switching control unit 200 has a CPU (RISC processor) 201; memory (two-port RAM) 202 and 205; work memory (RAM) 203; instruction storage memory (ROM) 204; and parallel/serial converters (PS) 2061 to 2064.
The memory 202 stores control data sent from the host processor 1. FIG. 24 shows control data stored in memory 202.
The control data sent from the host processor 1 is stored in memory cells in order from a prescribed address (here, address X). Each memory cell holds 32 bits. In the figure, the right end of each memory cell is the first (lowermost) bit, and the left end is the 32nd (uppermost) bit.
Control data has line control data (A, B, C, D, X, Y), provided in a plurality of channel units (or ring units) (in FIG. 24, there are 24 channel units), and line setting data (channel setting data), provided for each channel.
Line control data includes two bits of node fault data A (hereafter also called “BSC”); one bit of ring bridge trigger data B (hereafter also “BR”); one bit of ring switch trigger data C (hereafter also “SW”); one bit of control data D for device testing (hereafter also “TESTcont”); one bit of span switch trigger data X (hereafter also “Spanswcont”); and one bit of span bridge trigger data Y (hereafter also “Spanbrcont”).
In FIG. 24, the line control data is provided in 24channel units. Specifically, one set of line control data is provided for channels ch1 to ch24, directed from the west (input) side of the node toward the east (output) side (hereafter “east side”), and one set of line control data is provided for channels ch1 to ch24, directed from the east (input) side of the node toward the west (output) side (hereafter “west side”).
When there are twenty-five or more channels, a set of line control data is similarly provided for the 24 east-side channels ch25 to ch48, and a set of line control data is provided for the 24 west-side channels ch25 to ch48.
The node fault data A (BSC) indicates that no fault has occurred when A=0, indicates occurrence of a fault at another node when A=1, indicates that a fault has occurred in the east-side channel of the node itself when A=2, and indicates that a fault has occurred in the west-side channel of the node itself when A=3.
The ring-bridge trigger data B (BR) indicates that no ring bridge is to be executed when B=0, and that a ring bridge is to be executed when B=1. The ring-switch trigger data C (SW) indicates that no ring switch is to be executed when C=0, and that a ring switch is to be executed when C=1. The device testing control data D (TESTcont) indicates that device testing is not performed when D=0, and that device testing is performed when D=1.
The span-switch trigger data X (Spanswcont) indicates that no span switch is to be executed when X=0, and that a span switch is to be executed when X=1. The span-bridge trigger data Y (Spanbrcont) indicates that no span bridge is to be executed when Y=0, and that a span bridge is to be executed when Y=1.
Line setting data includes, as control data elements, one-bit NUT channel (channel which does not perform salvaging by means of the BLSR) setting data E (hereafter also called simply “NUT”); one-bit submarine switch control data F (hereafter also “SubmarineSW”); one-bit ring-switch control data G for device testing (hereafter also “RingSWcont”); one-bit submarine bridge control data S (hereafter also “SubmarineBR”); and one-bit ring-bridge control data T for device testing (hereafter also “RingBRcont”). These line setting data bits are provided for each channel.
When the data bit E (NUT) is set to E=0, the corresponding channel is set to a channel which is salvaged by means of BLSR, and when set to E=1, the corresponding channel is set to a channel which is not salvaged by means of BLSR. When the data bit F (SubmarineSW) is set to F=0, submarine switching is not performed; when set to F=1, submarine switching is performed.
When the data bit G (RingSWcont) is set to G=0, ring switching for device testing is not performed; when set to G=1, ring switching for device testing is performed. When the data bit S (SubmarineBR) is set to S=0, submarine bridging is not performed; when set to S=1, submarine bridging is performed. When the data bit T (RingBRcont) is set to T=0, ring bridging for device testing is not performed; when set to T=1, ring bridging for device testing is performed.
This line control data and line setting data is converted into control signal data and stored in the memory 205.
As shown in FIG. 25, the control signal data includes, as data elements, ring-switch control data H (hereafter also “RingSW”); ring-bridge control data I (hereafter also “RingBR”); span-switch control data J (hereafter also “SpanSW”); and span-bridge control data K (hereafter also “SpanBR”). This control signal data is provided for the east side of each channel, and for the west side of each channel.
The east-side ring-switch control data H is sent to the selection circuit 41 of the ring-switch unit 4; the west-side ring-switch control data H is sent to the selection circuit 42 of the ring-switch unit 4. The selection circuits 41 and 42 select and output the main signal on the first input (work line) side when H=0, and select and output the main signal on the second input (protection line) side when H=1.
The east-side ring-bridge control data I is sent to the selection circuit 61 of the ring-bridge unit 6; the west-side ring-bridge control data I is sent to the selection circuit 62 of the ring-bridge unit 6. The selection circuits 61 and 62 select and output the main signal on the first input (work line) side when I=0, and select and output the main signal on the second input (protection line) side when I=1.
The east-side span-switch control data J is sent to the selection circuit 31 and AIS insertion circuit 33 of the span-switch unit 3; the west-side span-switch control data J is sent to the selection circuit 32 and AIS insertion circuit 34 of the span-switch unit 3. The selection circuits 31 and 32 select and output the main signal on the first input (work line) side when J=0, and select and output the main signal on the second input (protection line) side when J=1. The AIS insertion circuits 33 and 34 insert and output an AIS when J=1, and do not insert and output an AIS when J=0.
The east-side span-bridge control data K is applied to the selection circuit 51 of the span-bridge unit 5. The west-side span-bridge control data K is applied to the selection circuit 52 of the span-bridge unit 5. The selection circuits 51 and 52 select and output the main signal on the first input (work line) side when K=0, and select and output the main signal on the second input (protection line) side when K=1.
If processing to convert line control data and line setting data into control signal data H through K, which is conventionally executed in hardware, is replaced without modification by software processing, the software processing is described by the flowchart as shown in FIG. 26. This flowchart shows only the portion in which the east-side ring-switch control data H is generated. FIG. 27 is an example of a program, written in the C programming language and in the assembly language for a RISC processor, to perform the processing of this flowchart. This program is stored in the instruction storage memory 204.
The CPU 201 first initializes the variable i, used as an index to specify the channel number, to 1 (S101), and then judges whether the NUT of channel chi is 0 or not (S102).
If the NUT of channel chi is not 0 (“N” in S102), the CPU 201 sets RingSW (data H) for channel chi to 0 (S109), and if the NUT of channel chi is 0 (“Y” in S102), judges whether TESTcont is 0 or not (S103).
If TESTcont is not 0 (“N” in S104), the CPU 201 sets RingSW to the value of RingSWcont (Silo), and if TESTcont is 0 (“Y” in S104), judges whether SubmarineSW for channel chi is 0 or not (S104).
If SubmarineSW is not 0 (“N” in S104), the CPU 201 sets RingSW to 1 (S111), and if SubmarineSW is 0 (“Y” in S104), judges whether BSC is 2 (“10” in binary notation) and SW is 1 (S105).
If BSC is 2 and SW is 1 (“Y” in S105), the CPU 201 sets RingSW to 1 (S106), and otherwise (“N” in S105) sets RingSW to 0 (S112).
Thereafter, the CPU 201 increments the variable i by 1, and generates the data H for the next channel (S107, S108). This processing is repeated a number of times N equal to the number of channels (for example, N=24).
In this way, if conventional hardware processing is realized in software without modification, processing in channel units is repeated for the number of channels accommodated, so that processing time is lengthened, and there is the problem that processing cannot be performed within the allowed time.
For example, as shown in FIG. 27, when using instructions for a RISC processor, twenty-two steps per channel are required. Generation of a ring-bridge control signal I involves similar processing, and so the number of steps is approximately the same. Hence when executing a ring switch and ring bridge, the number of steps is approximately 44.
In an OC-192 4BLSR system, processing for 768 channels must be performed, and so a total of 768×44=33792 steps are required.
If the operating frequency of the CPU 201 is 100 MHz, and one clock cycle is required for execution of one step, then 33792×10 (nanoseconds)=338 (microseconds) is required.
This is only one example of the time required for generation of ring-switch control data H and ring-bridge control data I; in actual processing, RIP (Ring Interworking on Protection) and other functions are realized, so that processing is more complicated, and still more steps are required.
Consequently when realizing the functions of a line switching control unit 200 in software, there is the concern that the allowable time from the occurrence of a fault until the completion of switching (for example, 50 milliseconds) may be exceeded.
In order to speed software processing, the CPU operating frequency may be raised, the CPU bandwidth (number of processed bits) may be increased, or a multiprocessor architecture may be adopted; however, these measures result in increased power consumption, and are not preferable in that they result in increases in hardware scale and costs.
Hence there is a need to reduce the number of steps required for processing to generate the control signal data H, I and similar, to shorten the time required for processing.